This application claims priority from Korean Patent Application No. 2003-0053625, filed on Aug. 2, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.
1. Field of the Disclosure
The present disclosure relates to a method of manufacturing a semiconductor device, and a semiconductor device manufactured using the same. More particularly, the present disclosure relates to a method of manufacturing a high performance semiconductor device with low sheet resistance and excellent thermal stability, and a semiconductor device manufactured using the same.
2. Description of the Related Art
With increasing integration of semiconductor devices, semiconductor devices with linewidth of less than submicrometer size are increasingly in demand. Accordingly, influences of contact and sheet resistance on operation characteristics of semiconductor devices become increasingly important.
A silicide process has been widely used to form silicide contacts on the gate and source/drain of metal oxide semiconductor field effect transistors (MOSFETs) or on the emitter, base, and collector of bipolar devices. A silicide process is a process of forming a stable metal compound by reacting silicon and metal and reduces the sheet and contact resistance at contact regions. The process is useful in obtaining high performance semiconductor devices. Meanwhile, silicide process or a self-aligned silicide process has been used in fabrication of many logic devices. However, in the fields of next generation high-speed complementary metal oxide silicon (CMOS) logic devices and embedded dynamic random access memory (DRAM) devices formed by combination of logic devices and DRAM devices, there has been a need for the development of new silicide materials that can provide more excellent characteristics than TiSi2 and CoSi2 which have been mainly applied in conventional silicide processes.
Recently, nickel monosilicide (NiSi) has been proposed and studied as a silicide material suitable for a next generation ultralarge-scale integrated (ULSI) semiconductor process. The NiSi can be formed with low resistivity of about 14 μΩ·cm by only one annealing process. A film made of the NiSi exhibits no increase of resistivity even on narrow (1 μm in linewidth, for example) poly-Si gates. Furthermore, since NiSi does not react with nitrogen gas used during annealing and almost all of deposited Ni reacts with Si, the amount of Si consumed during the reaction can be adjusted precisely. Still furthermore, the NiSi has other valuable merits, such as low reactivity of it with dopants in the source/drain region and less Si consumption for formation of the NiSi with a constant thickness, when compared with the Si consumption for formation of other silicide, in particular, CoSi2, which is the most widely used silicide. Therefore, NiSi is silicide that is very suitable for next generation ULSI devices.
However, when used for actual Si devices, the NiSi has a serious problem of low thermal stability at high temperature during a succeeding annealing process. Many solutions for such a problem have been suggested.
Mangelinck et al. reported that when Ni, inclusive of 5 atomic % platinum (Pt), is deposited on a Si substrate, followed by annealing, an NiSi film with enhanced thermal stability is formed [D. Mangelinck, J. Y. Dai, J. S. Pan, and S. K. Lahiri, Applied Physics Letters, 75, (1999) pp. 1736]. However, due to the added Pt, there is a problem in that an electrically active defect is observed in n-type Si. Maa et al. proposed insertion of an iridium (Ir) or cobalt (Co) layer between an Ni layer and a Si substrate [U.S. Pat. Nos. 6,468,901 and 6,534,871, and J. S. Maa, Y. Ono, D. J. Tweet, F. Zhang, and S. T. Hsu, Journal of Vacuum Science & Technology A, 19 (2001) pp. 1595]. However, in case of using the Ir layer, since Ir is not easily etched during etching, it is difficult to actually apply the Ir layer to Si devices. On the other hand, in case of using the Co layer, due to high reactivity of Co and Si, a Co-silicide spike is easily formed. As a result, generation of abnormal junction leakage current may increase.
U.S. patent application Laid-Open Publication No. US 2002-0045307 A1, issued to Kittel et al., discloses a method of manufacturing low resistance Co-, W-, Mo-, Ni-, Pt, and Pd-silicide, comprising: inserting refractory metals such as Mo, Co, W, Ta, Nb, Ru, and Cr into a Si-containing layer intended for silicide formation and depositing Co, W, Mo, Ni, Pt, and Pd on the Si-containing layer, followed by annealing. Here, ion implantation, physical vapor deposition (PVD), or chemical vapor deposition (CVD) is used for the insertion of the refractory metals into the Si-containing layer. However, according to this method, since the insertion of the refractory metals into the Si-containing layer is carried out after formation of a gate material, silicide with enhanced characteristics can be formed only on a gate region. For this reason, there is a problem in that a source/drain region, which can greatly influence operation characteristics of Si devices, cannot have good silicide. Therefore, there is a need for development of more improved processes for formation of NiSi to be applied to actual Si devices.